Many integrated circuits and semiconductor devices utilize an array of bumps, such as ball grid arrays (BGAs), for surface mounting packages such as printed circuit boards (PCBs). Package pin structure, such as C4 bumps or microbumps (as used in stacked silicon applications), may be used to conduct electrical signals between a channel on a chip or other package device, and the integrated circuit board (e.g., PCB), on which it is mounted.
As channel data rate requirements increase (e.g., from 14 Gbps to 28 Gbps and 56 Gbps), there is an increased need to be able to reduce the insertion loss of the channels in order to support the higher data rates. Channel insertion loss may be caused by a variety of factors, such as feature size, length of routings and transmission lines, and parasitics associated with the BGA bumps.
Thus, a package pin structure having a lower insertion loss so as to be able to support higher channel data rates may be desirable.